Research Area Hardware Systems

Hardware faults can occur during the design phase as well as during manufacturing. In contrast to software, hardware faults cannot be corrected afterwards. This is why researchers are working on developing automated test methods, which can prove safety and correctness of the resulting product during the design phase. Furthermore, increasing the efficiency of the design process while keeping the reliability of the system is an issue.

Our expertise includes test generation and formal verification across the whole design process and different levels of abstraction (e.g. gate level, RTL, ESL), technical documentation, and hardware software codesign.

Contact

Prof. Dr.-Ing. Daniel Große
Senior Researcher
+43 732 24684560

Our Technical Expertise

• Technical documentaion, UML/OCL, visualisation
• System C, hardware software co-design
• Formal verification, e.g. quivalence check, property check, debugging
• Test generation/ATPG, timing and path analysis