The project "Hardening the Supply Chain through Open Source, Trusted EDA Tools and Processors (HEP)" focuses on RISC-V processors. RISC-V is a new, open and free instruction set architecture, forming the interface between software and hardware. RISC-V is a promising open source standard for all application areas. The aim of the project is to develop a hardened, formally verified RISC-V processor with special cryptographic hardware accelerators. The hardening of the chip aims to provide as few vulnerabilities as possible for physical attacks on the system. The modifiability of a verified RISC-V processor offers the potential to enable secure applications for the Internet of Things and to establish a new standard in the automotive industry, for example. Therefore, the project will also develop and implement extensions for open-source circuit design tools - so-called Electronic Design Automation (EDA) tools - which integrate hardening measures into the circuits in an automated way. In addition, it will be investigated how hardware Trojans can be inserted from design to production and what protective measures are possible against such attacks.
|Duration:||Mar 1, 2021 - Feb 29, 2024|
IAV GmbH Ingenieursgesellschaft für Auto und Verkehr
Elektrobit Automotive GmbH
Fraunhofer-Institut für Sichere Informationsanlagen (SIT)
Ruhr-Universität Bochum, Lehrstuhl für Security Engineering
Technische Universität Berlin, Department Security in Telecommunications
|Research area:||Hardware Systems Security Software Systems|